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Abstract

This paper emphasizes on proposing a dynamic voltage restorer–based superconducting magnetic storage devices have utilized to power quality issues. Dynamic voltage restorer can be used for different topologies of the inverter. The conventional topology of dynamic voltage restorer possessing voltage source inverter or Z-source inverter is modified into a switched coupled inductor inverter which has the clear edge in power transfer over the former. The versatility of the controller is enhanced by this work by deploying a fuzzy combine discrete wavelet transforms. The proposed system in this paper, switched coupled inductor inverter–based dynamic voltage restorer-superconducting magnetic storage devices on mitigating the interruption, harmonics and voltage sag/swell. The operating of switched coupled inductor inverter has buck/boost function capability and reduced number of passive components. Due to digitalization, higher utilization factor and reduced harmonic content, controller of fuzzy logic–space vector pulse width modulation techniques with filter application of discrete wavelet transform is used to operate of switched coupled inductor inverter. The hysteresis controller is used to perform the superconducting magnetic storage devices device, has the ability in the storage of real power with high energy density and protects the consumer from grid fluctuation. To detect the power quality disturbances quickly response and improve the compensation capability of dynamic voltage restorer-superconducting magnetic storage devices. The whole of the suggested system is simulated in MATLAB/Simulink and realized as a prototype whose control pulses are duly generated and fed by dSPACE 1104 controller.

Keywords

Power quality hysteresis current controller space vector modulation techniques fuzzy logic controller discrete wavelet transform superconducting magnetic storage devices

Introduction

Maintaining the quality of power is one of the fundamental factors on both the transmission and distribution side. Custom power devices like dynamic voltage restorer (DVR), unified power quality conditioner (UPQC) and dynamic static synchronous compensator (DSTATCOM) are involved in the enhancement of power quality (PQ). The instantaneous energetic response of DVR makes it be a valid sequence compensating device. DVR consists of injecting transformer where high-voltage windings existed which is associated with a distribution side, and low voltage windings are attached to the switched coupled inductor inverter (SCII), along with superconducting magnetic storage devices (SMES). The main reasons for PQ problem rise are the custom of drives, machines and electronics equipment in the distribution system. To overcome, DVR has to be used to mitigate simultaneously for harmonics and voltage sag/swell.

In Zheng et al.,¹ for mitigating voltage disturbances, a new concept of instantaneous d-q transform detected and device of 0.3H/1.76K-A SMES used to compensate mega watts–level voltage disturbances. In this method, it is not accurate to get a sinusoidal waveform in output voltage and current. Voltage sag condition, a fault occurs in the system when an unsymmetrical is not adequately mitigates for the harmonics content of voltage source converter (VSC) were accompanying with SMES. Discrete wavelet transform (DWT) using Butterworth passive LC filter for operating DVR to improve PQ issues under different abnormal conditions. The implementation of a digital filter as Butterworth passive LC filter is used to detect the transient voltage and steady-state harmonic distortion.²

DVR can be recognized using impedance-source inverter (ZSI) topology to alleviate the voltage disturbance such as voltage sag/swell, voltage imbalance, voltage perturbation and harmonic distortion. Space vector pulse width modulation (SVPWM) generate pulses has operated to the inverter of ZSI and injecting voltage through a transformer. SVPWM to be effectiveness, allow high utilization factor of DC bus voltage and reduce harmonic content in the distribution network.³ A switch coupled inductor (SCII) has direct current (DC) – alternate current (AC) inverter features of advanced voltage again than existing quasi-ZSI. It has lesser passive components and less active stress.^4,5

SMES can be used for a numerous application such as frequency control application, PQ, dynamic response, stabilization. However, here we dealt with PQ application of SMES based on DVR for voltage sag/swell and interruption compensation. The simulation is to compete with the accuracy of the impedance parameter of the SMES system. The mathematical representation is based on the frequency domain using three-dimensional (3D) volume integral formulations for solenoid and non-solenoid are done in Rubinacci and Zamboni.⁶ In Yunus et al.,⁷ a SMES integration of wind turbines installed the modern power grid. The proposed system of SMES is to improve the dynamic performance of wind energy conservation by means of a doubly fed induction generator (DFIG) for the duration of voltage sag/swell. In this case of disadvantage, it is more harmonics and maximum overshoot of DC bus voltage. The current inductor has emulated SMES. Three phases (3φ) voltage source inverter (VSI) used to normalize AC voltage and two bidirectional DC–DC converters to control the energy storage system for charging and discharging. DC bus signalling and voltage sag control have been used to routinely control power from the magnetic energy storage system for the duration of short-duration, voltage sag, while the battery is used to provide power for the duration of the longer term, low-power under voltages.^8,9

PQ issues are classified into various methods to be extracted and analysed. For the signal processing algorithms are the Fourier transform (FT), wavelet transform, short time Fourier transform (STFT) and so on, have been utilized in the proposed system of existing methods. Wavelet transform (WT) has been used for recognition and enhancing of PQ disturbances due to its valuable properties like time–frequency limitation. The filters are suitable to extract a signal in a specified bandwidth, that is, high-pass filter (HPF) and low-pass filter (LPF). The WT is used to suppress harmonic content in the power system. This method is used to decompose the signal at a different frequencies that occurs in power system transients. In the performance of PQ, classifications are carried out in Li et al.,¹⁰ Moradlou and Karshenas,¹¹ Ho et al.,¹² Lam et al.,¹³ Ghosh and Ledwich,¹⁴ Kumar et al.,¹⁵ Venkatesh et al.,¹⁶ Tse,¹⁷ Santoso et al.¹⁸ and Kamthekar et al.¹⁹ DWT is a practical computational method that emphasizes considering the choice of wavelet families. It is meant to identify and rapidly rectify poor PQ signal such as interruption, switching transient, voltage sag/swell and harmonics. In Guo et al.,²⁰ the proposed topology of a 0.5 MVA/1 MJ superconducting magnetic energy storage system-based DVR will not only compensate voltage deviations during voltage sag, but will also work as a reactive power compensator and harmonic content to compensate both current and voltage harmonics as well as the reactive power of the downstream load in regular operation.

This paper presents DVR-based SMES with techniques of hysteresis controller–fuzzy controller, along with the filter application of DWT. DWT used for decomposing and reconstruction of the signal using multi-resolution process. It has an excellent ability to detect and extract frequency, and widely used in the voltage sag, voltage swell, interruption and harmonics. The SCII improves buck–boost function, and it implements an extra shoot through the state on the inverter bridge. It has similar principles of ZSI; it requires a smaller number of passive components with more extra shoot through capability and lesser active voltage stress at same voltage gain, to sustain minimum voltage and current stress at a specified operating point. When a fault occurs on the distribution system, operate to replenish the DC link capacitor through a SMES system. The design of two controllers, hysteresis current controller (HCC) is compared to the voltage across (V_dc) with the reference dc voltage (V_{dc, ref}), generate PWM signal given to the DC–DC chopper. They required constant DC voltage or without pulsating DC voltage for the inverter. The inverter is used to control using fuzzy logic controller (FLC) with SVPWM techniques and filter of DWT. FLC is to contrast the actual yield voltage with a set of input and reference voltage. The output signal is input to SVPWM generator which produces pulses to the inverter switches. The inverter voltage injected through a series transformer which eliminates harmonics and mitigates voltage sag, swell and interruption.

System description of DVR

DVR is connected SCII that injects the voltage during PQ issues. DVR typically installed in the distribution network and to provide the more reliable device. The unit of power system parts is SCII, series injecting transformer, energy storage system as a SMES system with a DC–DC chopper and filter application of DWT. In this proposed method, the operation of DVR instead of a traditional inverter is replaced by SCII and SMES system, as shown in Figure 1.

Figure 1.

Schematic diagram of DVR-SMES.

Operation of SCII

SCII operates at a high voltage in buck–boost function capability and gives higher gain. It has similar principles to ZSI; it requires a smaller number of passive components with greater extra shoot through capability. SCII consists of a diode and mutual inductance with a capacitor connected in one winding during normal state and during the shoot through the state, as shown in Figure 2(a) and (b), respectively.

Figure 2.

(a) SCII during a normal state and (b) SCII during shoot through the state.

Under normal conditions, current flows from the source, charging the inductors and returns through the MOSFET. During this period, the capacitor is also charged by the inductor winding L₂. During the shoot through the period, the diode is switched off, and no current flows from the source. The charged capacitor discharges and makes L₂ winding to charge with the current flowing through the MOSFET again. The total energy in the inductors during the switching period is maintained at a constant voltage.

Mathematical modelling of DVR

From the DVR diagram, to reduce complication of modelling, assume transformer turn ratio is 1.1. The grid connected SCII is shown in Figure 1, where V_in and I_f are voltage and current of SCII, V_c and I_c are voltage and current of filter, V_inj and I_inj are injecting voltage and current. Using Kirchhoff’s law

$I_{f} (t) = I_{c} (t) + I_{inj} (t) = C_{f} \frac{d}{dt} V_{inj} (t) + I_{inj} (t)$ (1)

$V_{in} (t) - V_{inj} (t) - R_{f} I_{f} (t) - L_{f \frac{d}{dt} I_{f} (t) = 0}$ (2)

Manipulation of these equations, we get

$y (t) = Cx (t)$ (3)

where C is capacitor of DC link.

By Clarke’s transformation, equations (1) and (2) can be written as

$x (t) = [I_{f}^{\propto}, I_{f}^{β}, V_{inj}^{\propto}, V_{finj}^{β}]^{T}$ (4)

$v (t) = [V_{inj}^{\propto}, V_{finj}^{β}]^{T}$ (5)

SMES operating principle

A SMES system consists of a sizable superconducting coil and DC–DC chopper. A larger superconducting coil contains a cryostat or Dewar comprising vacuum vessel that cools the coil. A cryogenic system is also used to keep a constant temperature and well maintained below a critical value. An AC/DC converter has its two methods; the first converts electrical energy from AC to DC and other one is to charge and discharge coil. During operation, the magnet coils have to remain in superconducting status. SMES coil is specific to rate and ecological impact by falling fuel utilization and discharge. It has fast response capability and higher efficiency other than a storage system.

SMES is a designed model as shown in Figure 3 with its simple principle. SMES could connect SCII with the DC–DC chopper. A bypass switch is minimized as the energy losses when the coil is on the standby method. When an entity is on standby, the current coil is kept constant, liberated of storage level, by altering the chopper duty cycle of 50% consequence in net voltage across the superconducting winding to be zero. Both charging and discharging are applicable. When charging cycle, the solenoid coil has to be placed across DC source. When a certain amount of energy is stored in the coil, then DC source disconnected and solenoid coil shorted during superconductor substance. Therefore, a current constantly flows in the course of the coil with decaying and the energy is stored in the solenoid. For transient suppression scheme can be optimized to reduce the voltage/current is used as MOV (metallic oxide varistor) and surge capacitor. MOV is to limit the overvoltage and tuning current sharing inductance in SMES system. A SMES system, integrated system of DVR-aided SCII with SVPWM techniques for simulating in MATLAB/Simulink.

Figure 3.

SMES system.

The control strategy of SCII and SMES system

The control scheme approach of SMES with a DC–DC chopper through SCII configuration to mitigate the voltage sag/swell, interruption and harmonics. The DC–DC chopper controlled using HCC and inverter controlled using FLC with SVPWM techniques. SVPWM is advantages due to the deployment of the DC bus voltage and which allow more in-depth sag compensation. However, SVPWM enables the likelihood to mitigate unbalanced faults condition The HCC is mostly used because of its simplicity, inattentiveness to load parameter variation, energetic response and characteristic of maximum-current-limiting. The underlying functioning of the HCC based on developing the switching signals from the contrast of the actual phase current with a reference current connected with that phase. The effect of interference between phases can show the way to high switching frequencies. The advantages of the hysteresis method, this phase dependence is capable of reducing using the phase-locked loop (PLL) technique en route to keep the DC–DC chopper switching at a frequency level. The proposed SMES with a supplementary PLL controller is shown in Figure 3. The HCC has compared the voltage across (V_dc) with the reference DC voltage (V_{dc, ref}), generate PWM signal given to the DC–DC chopper. It is required for constant DC voltage or without pulsating DC voltage for the inverter. The inverter is used to control using FLC with SVPWM techniques and filter of DWT. The space vector is a highly effective way to generate the pulses. With the help of SVPWM control, can achieve high utilization of DC voltage through an inverter of SCII.

Digital filtering is the technique of DWT used to decompose the signal into a different level. A discrete signal can be filtered by the filter of analysis bank and synthesis bank at three-level structures as shown in Figure 4. DWT is used to separate the frequency content of the input signal. An input signal of load voltage V_abc is transmitted as a vector using a buffer given to the system of DWT structure, as shown in Figure 4(a). A DWT is used to separate the decomposing and reconstruction signal using the multi-resolution process, as shown in Figure 4(b) and (c). DWT developing the coefficient are d₁, d₂, d₃, a₁, a₂ and a₃ as shown in Figure 4(b) and (c). The computation is obtained by the following equations (equations (6)–(11)). The output of the filter for each signal contains half frequency content. The sampling frequency includes an input signal for the LPF and HPF; this structure is called DWT. Therefore, down sampling and an up sampling factor of 2, and denoted by 2↑ and 2↓, respectively, are applied to the output of the filter in the analysis and synthesis bank

$d_{1} (2 k) = \sum_{n = 0}^{L - 1} h (n) x (2 K - n)$ (6)

$d_{2} (4 k) = \sum_{n = 0}^{L - 1} h (n) xi 1 (4 K - 2 n)$ (7)

$d_{3} (8 k) = \sum_{n = 0}^{L - 1} h (n) xi 2 (8 K - 4 n)$ (8)

$a_{1} (2 k) = \sum_{n = 0}^{L - 1} g (n) x (2 K - n)$ (9)

$a_{2} (8 k) = \sum_{n = 0}^{L - 1} g (n) xi 2 (4 K - 2 n)$ (10)

$a_{3} (8 k) = \sum_{n = 0}^{L - 1} g (n) xi 2 (8 K - 4 n)$ (11)

where L is filtered length.

Figure 4.

Structure of DWT: (a) block diagram of controller, (b) decomposition and (c) reconstruction.

FLC

The discrete voltages are taken and subtracted from their respective reference voltages generated considering the load advance angles. Which gives the error signal for each component? The change in error signal obtained differentiating the error signal. FLC is known for being a dynamic and intelligent tool for solving the non-linear problem. Similar to the conventional controller, FLC does not need a mathematical model for the system. Understanding of the complete system its control requisite is comparative for framing the rule base. The design of the FLC is made using the information/data flow as input. It followed by getting a process with a decision-making engine, its following control signal attained along with the defuzzification engine. Figure 5 shows the different stages of FLC.

Figure 5.

Block diagram of FLC.

Multiplexing of the error voltage (V_e) and its derivative (ΔV_e) can be done. Details provided as input to the FLC. Followed by the control signal for FLC given to the logic circuits intended for enabling generation of high-frequency pulses. The frequency variable pulses thus generated are provided to the switches Q1 and Q2 for tracking the voltage set. Figure 6 shows the details of the input supplied to FLC separated into seven membership functions, labelled as tabulated. Fuzzy control rules are developed in the course of the primary control knowledge without any consideration of the mathematical model of the plant. Table 1 shows the fuzzy rule base. Simple linguistic rules that help the performance of the control action are tabulated in the rule base.

Figure 6.

Membership functions.

Table 1.

Fuzzy rule.

V_e/ΔV_e	NB	NM	NS	ZE	PS	PM	PB
NB	NB	NB	NB	NB	NM	NS	ZE
NM	NB	NB	NB	NM	NS	ZE	PS
NS	NB	NB	NM	NS	ZE	PS	PM
ZE	NB	NM	NS	ZE	PS	PM	PB
PS	NM	NS	ZE	PS	PM	PB	PB
PM	NS	ZE	PS	PM	PB	PB	PB
PB	ZE	PS	PM	PB	PB	PB	PB

Simulation results and explanation

DVR-aided SCII integrated with SMES coil module is simulated in MATLAB/Simulink as shown in Figure 7. When 3φ faults occur in the distribution system, due to this condition and loads becoming more sensitive in the form of voltage sag/swell, interruption and harmonics. Those problems are used to identify and alleviate the PQ issues. In the simulation, two control techniques used are as follows:

HCC for SMES coils.

FLC with filter of DWT techniques.

Figure 7.

Simulation of controller system with SCII.

DVR consists of SCII, injecting transformer and interface SMES coil with DC–DC chopper. SMES coil is charging and discharging at the period of 0.1–0.5 s. During this period, either sag or swell mitigating depends on controller techniques. HCC controlled the SMES system for charging and discharging across the DC link capacitor.

Voltage sag of 0.75 × 10⁴ V magnitude and 0.1–0.2 s duration occurred during balanced 3φ fault with fault and ground impedance value of 0.85 Ω is considered in the feeder. With steady-state operating condition, for which the peak voltage from source voltage reduces its nominal value of 1 × 10⁴ to 0.25 × 10⁴ V. When common DC link capacitor voltage through the inverter removes voltage sag and returns to steady state. The output voltages of sag condition, injecting voltage, voltage sag compensation without and with DWT filter are shown in Figures 8 –11.

Figure 8.

Voltage during sag.

Figure 9.

Injecting voltage.

Figure 10.

Voltage compensation without DWT filter.

Figure 11.

Voltage sag compensation with DWT filter.

An additional source added, and as a consequence of this, voltage swell of 0.5 × 10⁴ V magnitude and duration ranges from 0.2 to 0.3 s occurs. The steady-state operating condition, the peak value of the source voltage rises from a nominal value of 1.0 × 10⁴ to 1.5 × 10⁴ V. As required supply voltage to the load, common DC link capacitor voltage through the inverter removes the voltage swell and return to its steady state. The output voltage of waveform shows in volt with and without compensation shown in Figures 12 and 13, respectively.

Figure 12.

Voltage swell.

Figure 13.

Voltage compensation for swell.

Momentary interruption of 0.45 × 10⁴ V magnitude and duration ranges from 0.1 to 0.2 s is occurred during balanced 3φ fault with fault and ground impedance value of 0.01 Ω. With a steady-state operating condition, for which the peak voltage from source voltage reduces from its nominal value of 1 × 10⁴ to 0.1 × 10⁴ V. It is required for stable supply to the load, common DC link capacitor voltage through the inverter removes voltage interruption and returns to steady state. The output voltage in volt without and with compensation is shown in Figures 14 and 15, respectively. The charging and discharging for DC link voltage of 220 V required for constant voltage during fault condition is shown in Figure 16.

Figure 14.

Voltage interruption.

Figure 15.

Voltage compensation for interruption.

Figure 16.

DC link voltage

Table 2 summarizes the evaluated total harmonic distortion (THD) value at different fault conditions. A line–ground fault occurs in this system in the range of 70%–80%. Line–line faults and its event sort may be between 15% and 20%. Double line–ground faults and the event these faults are about 10% when compared with total system faults. DVR-based DWT gives the reduced THD value of 0.34% and 0.70% in Table 1 and results are found using fast Fourier transform (FFT) analysis as shown in Figures 17 –20.

Table 2.

THD value at different conditions.

Sr. no.	Fault condition	Types of disturbances	THD without filter (%)	THD with filter (%)
1	3-Phase faults (LLL-G)	Voltage sag	5.62	0.34
2	L-G	Interruption	1.08	1.70

THD: total harmonic distortion.

Figure 17.

Harmonic analysis during sag compensation without filter.

Figure 18.

Harmonic analysis during sag compensation with filter.

Figure 19.

Harmonic analysis during interruption compensation without filter.

Figure 20.

Harmonic analysis during interruption compensation with filter.

Experimental investigations

The prototype model of DVR with SCII-based dSPACE 1104 controller shown in Figurer 21 has feeder lines and a supply of 50 Hz, 230/50 V transformers. Two sensing transformers of 100/6 V are used for sensing voltage variation. Here, injecting transformers were used to injecting voltage to the inverter circuit. It converts the AC source to DC and stores energy in DC link between the feeders. It is given as an input to the converter and converts it into AC and injects it to the feeder by injection transformer. For inducing voltage sag, the load is increased using switches. A 50 V, 50 W resistive load is used as a load. Two loads were variable while one was a constant load. The configuration parameter for the prototype model is given in Table 3.

Figure 21.

Prototype module.

Table 3.

Component ratings.

Sr. no.	Components	Rating	Quantity
1	Input transformer	230/50 V	1
2	Injecting transformer	50/10 V, 5 A	1
3	Sensing transformer	100/6 V, 5 A	1
4	MOSFET (IRF540)	500 V, 20 A	4
5	DC link capacitor	2200 µF	1
6	Filter capacitor	1000 µF	1
7	Filter inductor	1 mH	1
8	Load	500 Ω, 5 W	6
8	Load	1 mH	2
9	dSPACE controller board	1104	1
10	Fluke metre analyzer	–	1

A single-phase DVR has two feeders each supplying 50 V obtained by a step-down transformer of ratio 230/50 V. The transformer is giving the single-phase input from the supply of 230 V. The transmission line has an inductance of 1 mH. The loads consist of a constant load and variable loads of 500 Ω, 50 W and 1 mH inductor. The load voltage is sensed by a potential transformer (PT-100/6V). To facilitate hardware and simulation embedded controller, hardware in loop control using dSPACE 1104 processor is deployed in this work. The dSPACE1104 performs a pivotal role in processing the feedback signals from respective feeders and render control signals to the appropriate inverter switches for compensation. The feedback signals, namely, the output voltage (V₀), the input voltage (V_in) and current, were detected by a voltage sensor and a current sensor (ACS 312), respectively. The sensed voltage is reduced to the ±5 V range to comply with the operating voltage range of the dSPACE 1104 processor. The voltage error is obtained through a comparison of the reference voltage and output voltage with the progression of the DWT-based FLC. The metal-oxide semiconductor field-effect transistor (MOSFET)s receive the PWM signals thus generated from dSPACE 11104 controllers through isolation and driver circuits were applied to the inverter switches.

The output of the hardware is shown in Figures 22 and 23 while the voltages shown were concerning time (s). The voltage sag/swell is created using a variable load. With the increase in the load, voltage sag is detected as 36.83 V (shown in Figure 23) and has injected by DVR. The voltage across feeder 2 is pumped to feeder 1 for compensating for the voltage sag with the help of the MOSFET-based inverters and DC link capacitor which forms the DVR circuit.

Figure 22.

Source voltage.

Figure 23.

Load voltage with sag.

The power flow between two feeders is connected with the DC link capacitor. The voltage across the DC link was measured. The PWM pulse has generated by comparing output voltage and reference voltage through a control circuit, as shown in Figure 24. The corresponding output results from feeder voltage and output current are 43.56 V and 190 mA, as shown in Figures 25 and 26, respectively. The prototype model of DVR with SCII of inverter voltage, feeder load voltage with compensation and feeder load current is shown in Figures 25, 27 and 28, respectively. This helped to compensate 50% solution of sag voltage effectively. In feeder, an output voltage with filter compensation as shown in Figure 28 of voltage will be 44.35 V and DC link voltage across the capacitor has been 31.68 V, as shown in Figure 29. Table 4 shows the results of prototype model.

Figure 24.

Pulse for inverter.

Figure 25.

Inverter voltage of SCII.

Figure 26.

Load voltage without filter compensation.

Figure 27.

Feeder load current.

Figure 28.

Output voltage with filter compensation.

Figure 29.

DC link voltage.

Table 4.

Prototype results.

	Sourcevoltage	Beforecompensation	PWMsignal	Injectingvoltage	After compensation	THD (%)
Feeder 1 (during sag condition)	50.69 V	36.83 V	4.72 V	6.34 V	43.56 V	3.21

PWM: pulse width modulation; THD: total harmonic distortion.

The THD, after compensation at load side, is found to be 3.21% of voltage harmonics and 2.39% of current harmonics using Fluke Power Quality Analyzer, as shown in Figure 30. The %HIAN has investigated the percentage of current harmonics order between the phase (A) and neutral (N) and has reduced to 3.21% of fundamental components. The %HING investigated the percentage of current harmonics order between the neutral (N) and ground (G) of fundamental components. %HVAN (%) for voltage harmonics is found to be 2.39% of fundamental components between phase (A) and neutral (N).

Figure 30.

Total Harmonic Distortion (THD)

When spectrum analysis has been done, third-order harmonics distortion is found to be 2.5%, fifth-order harmonics distortion as 0.4% and seventh-order harmonics as 1.2%. Third-order harmonic current as comparatively more than that of other order harmonics, due to single-phase circuits having neutral produces third harmonics. Hence, it is predominately higher than that of other order harmonics.

Conclusion

A single-phase DVR a PQ issue mitigating device has been proposed in this work. The concept of DVR with SCII mitigates PQ problems like voltage sag/swell, interruption and harmonics in the distribution side. The constraint element of DVR system regarding the power exchange between the feeders depends upon the load variation. DVRs are mitigating voltage sag/swell and THD value reduced to 5.62%, 0.34% and 1.08%, 0.70% of harmonic content during variation of a fault condition. The analysis shows that the DVR system gave a compensation of 60% solution of PQ problems like voltage sag/swell for a long duration. A prototype module of DVR has been demonstrated to be effective about PQ problem using a dSPACE1104 controller. The prototype model of THD value was found to be 3.21% of voltage harmonics and 2.39% of current harmonics using the fluke metre PQ analyser. Simulation and hardware results reveal that the suggested system is highly viable.

Footnotes

Declaration of conflicting interests

The author(s) declared no potential conflicts of interest with respect to the research,authorship and/or publication of this article.

Funding

The author(s) received no financial support for the research,authorship and/or publication of this article.

ORCID iD

P Sivaperumal

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