A design of Ethernet adapter for visible light communication (VLC) is proposed in this paper. Based on field-programmable gate array (FPGA) technology and Ethernet protocols, the design applies Ethernet to VLC channel, enabling two-way transmission between both channels, giving solution to the conversion of signal between different coding formats. 8B10B DC-balanced encoding/decoding is used for VLC transceivers to ensure reliable and stable communication. At 1000BASE-T duplex mode, the maximum real-time net data rate on the VLC channel is 300Mbps by sending and receiving Ethernet frames in point-to-point communication with optical transceivers using phosphorescent white light emitting diode (WLED).
ChenJ., Multi-platform build for combination communication in internet of things, Journal of Computational Methods in Sciences and Engineering15(2) (2015), 261–267.
2.
WuC.H.GaoZ.Y.LiH.L.ChenX.B.MaoX.R.LuH.M.WangJ.P.HeL.CuiS.G. and ChenH.D., Realization of OFDM modulation and demodulation for visible light communication based on FPGA, Optoelectronics Letters (13) (2017), 58.
3.
LiH.L.ChenX.B.GuoJ.Q. and ChenH.D., A 550 Mbit/s real-time visible light communication system based on phosphorescent white light LED for practical high-speed low-complexity application, Optics Express (22) (2014), 27203.
4.
YadavS.PandeyS. and GuptaA., Implementation of 8B/10B encoder-decoder for Gigabit Ethernet Frame, Elev-enth International Conference on Wireless and Optical Communications Networks (WOCN) (2014), 1.
5.
Cyclone IV Device Handbook Volume 2, https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/cyclone-iv/cyiv-5v2.pdf.
6.
7 Series FPGAs GTP Transceivers, https://www.xilinx.com/support/documentation/user_guides/ug482_7Series_GTP_Transceivers.pdf.
7.
AshrafiH.MousazadehM. and HadidiK., An 8B/10B encoder with 2GHz operating frequency (2016), IEEE 59th Inter-national Midwest Symposium on Circuits and Systems (MWSCAS) (2016), 1.
8.
WuA.JinX.DuX. and GuoS., A flexible FPGA-to-FPGA communication system (2017), 19th International Conference on Advanced Communication Technology (ICACT) (2017), 836.
9.
YangX.L.LiX.Q. and LiG.J., The design and implementation of parallel switch system simulation platform based on Java, Journal of Computational Methods in Sciences and Engineering16(3) (2016), 451–457.
10.
AstarloaA.LázaroJ.BidarteU.AraujoJ. and MoreiraN., FPGA implemented cut-through vs store-and-forward switches for reliable Ethernet networks, Design of Circuits and Integrated Systems (1) (2014).
11.
WindmannS. and JasperneiteJ., An FPGA based FIFO with efficient memory management, IEEE 20th Conference on Emerging Technologies and Factory Automation (ETFA), Luxembourg (1) (2015).
12.
KamalR. and Moreno ArosteguiJ.M., Design of a dynamic depth high-throughput multi-clock FIFO for the DSPIN (2015), 1st International Conference on Next Generation Computing Technologies(NGCT) (30) (2015).
13.
SahniK.RawatK.PandeylS.RawatJ. and TripathiS., Design and verification of 8b/10b encoder/decoder for USB 3.0 applications, International Conference on Computer, Communication and Control (IC4) (1) (2015).
